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EE Times: Engineer Writes Open-Source Register Generation Tool

Sep 07, 2002, 04:00 (2 Talkback[s])
(Other stories by Richard Goering)


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"An open-source tool created by an ASIC designer promises to automate the laborious process of generating Verilog code for processor registers. Developed by Chuck Benz, an independent contractor here, the tool is now available for downloading from Benz' Web site.

"The tool, csrGen, is a Perl script that automatically creates the control status registers (CSRs) that handle processor read/write access in ASIC or FPGA design. Users provide information about registers and fields, and csrGen produces RTL Verilog code.

"While most open-source EDA tools are offered by universities or vendors, an increasing number of tools have been developed and offered by individual engineers in recent months. These include RHDL, an HDL based on the Ruby programming language; a C-like verification language; and ChipVault, a utility that launches synthesis tools, tracks HDL files and manages hierarchy..."

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