BW: CynApps...Intros new release of Cynlib with 6X speed advantage...Nov 29, 1999, 20:09 (0 Talkback[s])
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"CynApps today announced a new version of Cynlib, its open-source C++ hardware design library and simulator, which boasts significant performance improvement. Additional upgrades include a VHDL version of the Cyn++ macro preprocessor, and a new "Hardware Modeler" bundle."
"Cynlib v1.1 now includes support for Windows NT and HP-UX platforms in addition to its existing support for Solaris and Linux. A new threads implementation has increased simulation performance, with recent benchmark results demonstrating a 6X speed advantage over CynApps' closest competitor. Complete benchmark results are available at www.cynapps.com."
"Cyn++, a simple bridge between traditional HDLs and C++ to ease the transition of logic designers to high-level design, is now available in both Verilog and VHDL "flavors." This C++ macro preprocessor enables HDL designers to easily use C++ for logic design. The preprocessor's output is standard C++, but this is transparent to the logic designer since the simulation and debugging environment is related directly to the Cyn++ code. Used in conjunction with Cyntax, a lint utility that automatically reports syntax and semantic errors, Cyn++ offers Verilog and VHDL coders an easy transition path to C++ hardware design."
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