[ Thanks to Douglas Eadline for this
link. ]
“The difference between theoretical power and what is actually
delivered is measured as processor efficiency. The more CPU cycles
used to get the data out the door by “filling the wire” due to
protocol and data transfer inefficiencies, the less cycles are
available for the application. When comparing latencies of
different interconnects, one needs to pay attention to the
interconnect architecture. 1usec latency “on-loading” interconnect
versus 2usec latency “off-load” solution is similar to a case when
one needs to decide between two cars that show the same horsepower
(i.e. CPU). Both engines are capable of 200 miles per hour, but the
first car, due to “on-loading”, limits the actual engine power to
75 miles per hour (the engine power must be used for other tasks).
The Second car has no limitations on the engine, but its wheels can
tolerate only 150 miles per hour. The knowledge on the wheels
tolerance (i.e. latency), as a single point of data, is definitely
misleading.”