[ Thanks to Jason
Greenwood for this link. ]
“Tensilica has revised its configurable, extensible processor
core for SoC (system-on-chip) design. Xtensa 6 supports tools that
generate hardware designs and toolchains from C/C++ algorithms, the
company says. The synthesizable, 32-bit RISC core also features 30
percent lower power, and a ‘no execute’ bit for high-security
embedded Linux designs.“Tensilica’s Xtensa cores are based on a proprietary 32-bit core
architecture with 16- and 24-bit instruction sets. These small
instruction sets offer higher code density and require less power
than 32-bit instructions, the company says, yet support powerful
branch instructions such as combined compare-and-branch and
zero-overhead loops, and bit manipulations including funnel shifts
and field-extraction operations. An optional FPU (floating point
unit) is available…”